Flash memory device can be coupled to other devices such as a flash memory controller over an interface. A single flash memory controller can be connected via the interface to multiple flash memory devices.
The interface can include multiple wires that are used to convey control and data between one or more flash memory devices and a flash memory controller.
Each flash memory device can support a single interface specification. The interface specification defines the physical configuration of the interface as well as an interface protocol that is supported by the flash memory device.
The interface protocol can define the commands that should be exchanged with the flash memory device, as well as the order and the timing of various control and data signals.
Referring to FIG. 1, an interface is illustrated as being connected between a flash memory controller 40 and two flash memory devices 20 and 30—all belonging to system 10. The interface includes a data bus for conveying addresses, commands or data signals (D[0:7] 17), and control signals such as address latch enable (ALE) 16, write enable (WEn) 13, read enable (REn) 14 and command latch enable (CLE) 15. These control signals are shared between the different flash memory devices.
A chip select signal (such as CE_0 11 and CE_1 18) is provided for each flash memory device. A ready/busy (RB) signal (such as RB_0 12 and RB_1 19) is provided for each flash memory device.
The flash memory controller can be equipped with various circuits that are arranged to execute different operations such as a read operation, a write operation, a program operation and an erase operation. Each of these circuits is responsible to complete the entire operation and each circuit is tailored to a single interface specification. Referring to FIG. 1, the flash memory controller 40 may include a read circuit 42, an erase circuit 44 and a programming circuit 46 that are tailored to a first interface specification that is supported by first and second flash memory devices 20 and 30. The read circuit 42 executes read operations, the programming circuit 46 executes write operations and the erase circuit 44 executes erase operations.
Different flash memory devices can support different interface specifications. Interface specifications can differ from each other by one or more parameters such as the type of commands, the timing of commands and the sequence of commands that are required for supporting an operation.
There are at least two interface specifications known as “ONFi” and “Toggle NAND” and there are also many other interface specifications that differ from those two interface specifications, some of which are unpublished.
There is a need to provide a flash memory controller that is capable of interfacing with flash memory devices that support different interface specifications.